1. Field
The present disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including an electro-static discharge protection device.
2. Description of the Related Art
A typical semiconductor device includes an electro-static discharge (ESD) protection circuit to protect semiconductor elements from an external ESD surge. The formation of a p+ diffusion region in a drain region at a deep portion of a substrate is known as a method for enhancing ESD robustness of an electro-static discharge element in an ESD protection circuit. In this known example, however, the AC characteristics vary during normal operation of an IO cell depending on the accuracy of the p+ diffusion region formation process. Accordingly, there is a demand for an ESD protection circuit having fixed AC characteristics and increased ESD.
In a prior art semiconductor device, a single gate electro-static discharge element is used to protect an input/output circuit from electro-static discharge. FIGS. 1 to 3 show a semiconductor device including an ESD-protection-driver circuit employing the single gate electro-static discharge element of the prior art.
As shown in FIG. 1, a semiconductor device 100 includes an input/output pad 110 coupled to an internal circuit 120 by wiring W10. The input/output pad 110 is also coupled to an ESD-protection-driver circuit 130 by the wiring W10. The ESD protection circuit/drive circuit 130 includes a plurality of single gate electro-static discharge elements M10 that are coupled in parallel to one another. Each electro-static discharge element M10 includes a ballast resistor R and an N-channel MOS transistor T10, which is coupled in series with the ballast resistor R.
Referring to FIG. 2, the single gate electro-static discharge element M10 includes a gate electrode 142 arranged on a substrate 140 of p− silicon or the like by way of a gate oxidation film. A source region 145S and a drain region 145D including n+ diffusion regions are formed in the substrate 140 with the gate electrode 142 located in between. A source electrode 150 and a drain electrode 151 including silicide layers are respectively formed on the surfaces of the source region 145S and the drain region 145D. The drain electrode 151 is spaced apart from the gate electrode 142. A silicide block region 152, which does not include a silicide layer, is formed between the drain electrode 151 and the gate electrode 142. The silicide block region 152 serves as the ballast resistor R.
As shown in FIG. 3, the drain electrode 151 of each transistor T10 is coupled to metal wiring W1 through contact holes H1. The metal wiring W1 is coupled to the input/output pad 110. The source electrode 150 of each transistor T10 shown in FIG. 2 is coupled to metal wiring W2 through contact holes H2 as shown in FIG. 3. A ground potential Vss is applied to the metal wiring W2. The gate electrode 142 of each transistor T10 of FIG. 2 is coupled to metal wiring W3 through a contact hole H3 in FIG. 3. A gate voltage Vg is applied to the gate electrodes 142 via the metal wiring W3. The wiring of the gate voltage Vg may be coupled to the wiring of the ground potential Vss or an output terminal of a pre-buffer.
A case in which an ESD surge having a positive polarity is applied to the input/output pad 110 of FIG. 2 will now be discussed. In this case, the potential at the drain region 145D of the transistor T10 rises and causes an avalanche breakdown at the pn junction surface of the drain region 145D and the p− diffusion region of the substrate 140. This forms a pair of electron holes in the pn junction surface. The positive holes move into the substrate 140 and causes a flow of discharge current Ibh1. The discharge current Ibh1 raises the substrate potential. As a result, a parasitic bipolar transistor Tp1 including the p− diffusion region, the source region 145S, and the drain region 145D becomes electrically conductive in the substrate 140. When the parasitic bipolar transistor Tp1 becomes electrically conductive, a large current (arrow C in FIG. 2) flows between the drain region 145D and the source region 145S. As a result, the ESD surge applied to the input/output pad 110 is released into the wiring of the ground potential Vss to prevent the application of an ESD surge having positive polarity to the internal circuit 120. Furthermore, the potential at a common node does not significantly decrease due to the ballast resistor R even if one of the plurality of single gate electro-static discharge elements M10 becomes electrically conductive first. This prevents the current indicated by arrow C from concentrating at the single gate electro-static discharge element M10 that first becomes electrically conductive. Accordingly, when an ESD occurs in the ESD-protection-driver circuit 130, the parasitic bipolar transistor Tp1 becomes electrically conductive in all of the single gate electro-static discharge elements M10 that are coupled in parallel. This enables efficient discharging.
In this manner, the ESD robustness of the single gate electro-static discharge element M10 is increased by the silicide block region 152, that is, the ballast resistor R. However, the parasitic bipolar transistor Tp1 does not become electrically conductive until high voltage is applied to the single gate electro-static discharge element M10. This may result in the ESD damaging the internal circuit 120 before the ESD-protection-driver circuit 130 operates. Thus, there is a demand for an ESD protection circuit that starts to operate at a lower voltage.
Japanese Laid-Open Patent Publication No. 2004-15003 describes one example of an ESD protection circuit for solving such a problem. Such ESD protection circuit includes a p+ diffusion region formed immediately below the drain region 145D of each transistor T10 to partially overlap part of the drain region 145D in the depthwise direction. The p+ diffusion region is formed by injecting boron ion (B+) so that the impurity concentration of the p+ diffusion region becomes higher than that of the substrate 140. A depletion layer is formed in the pn junction surface of the drain region 145D and the p+ diffusion region. This depletion layer is narrower than a depletion layer that is formed in the pn junction surface of the drain region 145D and the p− diffusion region of the substrate 140. In such a configuration, an avalanche breakdown is likely to occur at the pn junction surface of the drain region 145D and the p+ diffusion region. This lowers the voltage that starts operation of the parasitic bipolar transistor.